(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to detect occurrences of mis-registration or shift of respective inner-layers that are created in a substrate.
(2) Description of the Prior Art
The increasing need for creating more extensive and more complex semiconductor device interconnect traces has, as one potential solution led to the application of low resistance metals, such as copper, for the interconnect traces. Another approach to increase Input/Output (I/O) interconnect capability has been to design chips and chip packaging methods that offer dependable methods of increased interconnecting of chips at a reasonable manufacturing cost. This has led to the development of Flip Chip Packages.
Flip-chip technology uses bumps (typically comprising Pb/Sn solders) formed over aluminum contact pads on the semiconductor devices and interconnects the bumps directly to a packaging media, which are usually ceramic or plastic or organic material based. The flip-chip is bonded face down to the package medium through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher levels of packaging, in which the packages are larger, and to more sophisticated substrates that have multiple layers of interconnect traces and that can accommodate several chips to form larger functional units.
The flip-chip technique, using an area I/O array, has the advantage of achieving a high density of interconnect to the device combined with a very low inductance interconnection to the package. The packaging substrate is generally used for Ball Grid Array (BGA) packages but can also be used for Land Grid Array (LGA) and Pin Grid Array (PGA) packages.
The mounting of a flip chip over the surface of a printed circuit board consists of attaching the flip chip to this board or to any other matching substrate. A flip chip is a semiconductor chip that has a pattern or array of terminals spaced around the active surface of the flip chip, the flip chip is mounted with the active surface of the flip chip facing the supporting substrate. Electrical connectors that are provided on the active surface of the flip chip can consist of Ball Grid Arrays (BGA) devices and Pin Grid Arrays (PGA) devices. With the BGA device, an array of minute solder balls is disposed over the active surface of the die for attachment to the surface of a supporting substrate. For PGA devices, an array of small pins extends essentially perpendicularly from the active surface of the flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other supporting substrate for attachment thereto. The flip chip is bonded to the printed circuit board by refluxing the solder balls or pins of the flip chip.
With continuously decreasing semiconductor device dimensions and increasing device packaging densities, the packaging of semiconductor device continues to gain increased importance. Packaging of semiconductor devices in many instances makes use of supporting substrates over the surface of which one or more semiconductor devices are mounted. To meet requirements of device connectivity, the substrate over which the semiconductor devices are mounted typically contains multiple overlying layers of interconnect traces. The upper and lower surfaces of the supporting substrate are provided with contact pads for the connection of the surface mounted devices and for the provision of contact balls to the interconnect traces of the substrate. Via holes through the substrate connect contact pads of the upper and lower surfaces. For purposes of efficiency and cost considerations, substrates are typically created in working strip form that are larger than the single unit substrates that are required for individual device packages. These working strip forms are after completion subdivided by sawing the working strip into individual BGA packages. Miss-registration of the inner layers of multi-layer must be carefully controlled and monitored in order to avoid problems of electrical shorts after the sawing has been completed. The invention addresses this concern and provides a method of easily measuring offsets of inner-layers after the individual substrates have been created.
U.S. Pat. No. 6,344,401 B1 (Lam) shows a method for a sawed signulated die and BGA package.
U.S. Pat. No. RE 36773 (Nomi) shows a plating method for nested plating trace on substrates.
U.S. Pat. No. 6,319,828 B1 (Jeong) shows a CSP with copper traces.
U.S. Pat. No. 6,184,570 B1 (McDonald, Jr. et al.) shows a related patent.
A principle objective of the invention is to provide a method of detecting and monitoring inner-layer miss-registration of a multi-layer configuration.
Another objective of the invention is to provide a method for monitoring the accuracy of alignment of inner layers that are from of a substrate.
A new method is provided for evaluating the alignment of inner layers of interconnect layers. A test pattern is inserted within and as part of the process of creating a saw singulated plastic ball grid array substrate. The test pattern comprises a point of reference for each inner layer of the substrate and multiple measurement points relating to the point of reference whereby each of these multiple measurement points is indicative of different amount of clearance or misalignment between the outer and the inner layers. By measuring electrical continuity or lack thereof between the point of reference relating to each inner layer pattern and the respective multiple measurement points and by identifying which of the multiple points is shorted to the point of reference, the mis-alignment of the inner layers of the saw singulated plastic ball grid array substrate can be determined.